Synthesis for Testability Techniques for Asynchronous Circuits

Our goal is to synthesize hazard-free asynchronous circuits that are testable in the very stringent hazard-free robust path-delay-fault model. From a synthesis perspective producing circuits satisfying two very stringent requirements, namely, hazard-free operation and hazard-free robust path-delay-fault-testability, poses an especially exciting challenge. In this paper we present techniques which guarantee both hazard-free operation and hazard-free robust path-delay-fault testability, at the expense of possibly adding test inputs, and give a set of heuristics which can improve hazard-free robust path-delay-fault testability without requiring such inputs. We also present a procedure that guarantees testability in the less stringent robust gate-delay-fault model.